The present invention relates to an erasure correction method and circuit and, more particularly, to an erasure correction method and circuit for erasure-correcting an error by plural error correcting codes.
As a method for improving reliability of a data processing system, error correction technology using an error correcting code having a capability of correcting errors in data is used in various types of data processing apparatus. In recent years, high-density recording to a recording medium, or a high data transfer rate or a high communication speed associated with a data processing apparatus increases error rates in data, and thus a higher correction capability for burst errors is particularly required. Accordingly, plural error correcting codes having higher error correction capabilities are added to data and two-dimensional or three-dimensional error correcting codes are constituted.
FIG. 3 is a diagram for illustrating a structure of a product code as an example of multiply-added error correcting codes. A data processing apparatus divides input data of d0,0, d0,1, d0,2, . . . , d1,0, d1,1, . . . every (nxe2x88x92s) pieces of data, constitutes a two-dimensional arrangement, and adds parities in each dimensional direction, thereby constituting a product code as shown in FIG. 3. An error correcting code obtained by coding data in a time series direction is referred to as an inner code. The inner code shown in FIG. 3 is a Reed-Solomon code having a code length of n, including (nxe2x88x92s) pieces of data and s parities added thereto. In addition, an error correcting code obtained by coding data which is discrete in a time series direction is referred to as an outer code. The outer code as shown in FIG. 3 is a Reed-Solomon code having a code length of m, including (mxe2x88x92t) pieces of data and t parities attached thereto.
When data having the product code structure as shown in FIG. 3 is reproduced, error correction for the data is usually performed for each inner codeword and subsequently performed for each outer codeword. The data for which the error correction is finished is read in the inner code direction and reproduced.
The erasure correction which is known as an error correction method gives a position of an error beforehand, thereby correcting more data than that in the normal error correction. At the normal error correction of the inner code, errors in (s/2) pieces of data can be corrected. However, when s pieces of data in one codeword include errors and erasure flags are set, and remaining (nxe2x88x92s) pieces of data have no error, errors in s pieces of data can be corrected by the erasure correction. This results from the fact that only the size of the error is required in the erasure correction, while the position and size of the error are required in the normal error correction.
In the case of a Reed-Solomon code, assuming that a code includes f demodulation errors where the erasure flags are set and includes e errors where the erasure flags are not set, when (f+2e)xe2x89xa6s, (f+e) errors can be erasure-corrected.
FIG. 4 is a block diagram illustrating a data processing apparatus utilizing an error correction method disclosed in Japanese Published Patent Application Hei.3-149923.
Data which is input to an input terminal 401 is coded by an outer code parity addition circuit 402 and an inner code parity addition circuit 403, further modulated by a modulation circuit 404, and recorded on a data recorder, i.e., a VTR 405 in this case. When the recorded data is reproduced from the VTR 405, the data output from the VTR 405 is demodulated by a demodulation circuit 406 into demodulated data, and input to an inner code erasure error correction circuit 408 and a symbol delay circuit 409. In addition, it is detected by a symbol pattern check circuit 407 whether the data output from the VTR 405 is a modulation code other than digital demodulation codes defined previously at the modulation time. When the data is other than the defined codes, it is output to the inner code erasure error correction circuit 408 as an erasure flag, as well as the number of erasure flags is counted for each inner codeword by an erasure symbol count circuit 410. In this case, when the number of the erasure flags is smaller than a reference, a switch 411 is switched to A to output data, to which the erasure correction of the inner code is performed, to an inner code error detection correction circuit 412. When the number of the erasure flags is larger than the reference, the switch 411 is switched to B to output data which is delayed by the symbol delay circuit 409. The inner code error detection correction circuit 412 performs the error correction of the inner code, and sets an erasure flag for a codeword which cannot be corrected. An outer code erasure error correction circuit 413 performs the erasure correction by using the erasure flag from the inner code error detection correction circuit 412, and sets an erasure flag for a codeword which cannot be corrected. Finally, a modification circuit 414 modifies data in which the erasure flag is set and errors may remain, and outputs reproduced data.
In the conventional erasure correction method, when errors cannot be corrected in correcting the inner code, the erasure flags are set for all data in the inner code. Therefore, at a time of correcting the outer code, the erasure flags are set also for data which is really correct. For example, when (s+1) erasure flags by the demodulation error are set in the inner code shown in FIG. 3, neither the inner code erasure error correction circuit 408 nor inner code error detection correction circuit 412 can correct errors. Therefore, the erasure flags are set for all the n pieces of data in the inner code. However, many pieces of data which are not erroneous are included therein. That is, the erasure flags are set even for correct data, thereby increasing a possibility that erroneous data cannot be corrected at the correcting time of the outer code and deteriorating the correction capability.
Further, when a burst error occurs, there is a high possibility of the erasure flags in excess of the number s of data which can be erasure-corrected in correcting the inner code being set. In this case, the inner code erasure correction using the erasure flags cannot be performed and the data cannot be corrected by the normal inner code error correction either.
It is an object of the present invention to improve a correction capability by using a demodulation error as an erasure flag for correcting plural error correcting codes and realize correction processings which are effective for burst errors.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
An erasure correction method according to the present invention for erasure-correcting an error by plural error correcting codes comprises steps of: demodulating modulated data into demodulated data having the plural error correcting codes added thereto; setting an erasure flag for a demodulation error at the demodulation time; and reading the demodulated data for each of the plural error correcting codes, and erasure-correcting errors in the demodulated data, including the demodulation error indicated by the erasure flag. Therefore, the erasure correction having a correction capability higher than that of the prior art which uses the demodulation error as an erasure flag only for the erasure correction of an inner code is realized.
The erasure correction method according to the present invention comprises a step of erasing the erasure flag for the demodulated data which is erasure-corrected, for each of the correcting codes, and using an erasure flag which is not erased at the erasure correction by a precedent correction code, thereby performing erasure correction by a subsequent correcting code. Therefore, the erasure flags are not incorrectly set to correct demodulated data and the erasure correction having a higher correction capability is realized.
The erasure correction method according to the present invention comprises a step of initially reading the demodulated data for each codeword of the outer code, thereby performing the erasure correction. Therefore, more errors can be erasure-corrected in data where burst errors are likely to occur.
The erasure correction method according to the present invention comprises steps of: reading the demodulated data for each codeword of the outer code to erasure-correct an error in the demodulated data, and erasing the erasure flag for the corrected demodulated data; and reading the demodulated data for each codeword of the inner code to erasure-correct an error using an erasure flag which is not erased by the outer code, and erasing the erasure flag for the corrected demodulated data. Therefore, the erasure correction having a higher correction capability is realized.
The erasure correction method according to the present invention comprises steps of: reading the demodulated data for each codeword of the inner code to erasure-correct an error in the demodulated data, as well as erasing the erasure flag for the corrected demodulated data; reading the demodulated data for each codeword of the outer code to erasure-correct an error by using an erasure flag which is not erased by the inner code, as well as erasing the erasure flag for the corrected demodulated data; and reading again the demodulated data for each codeword of the inner code to erasure-correct an error using an erasure flag which is not erased by the outer code, as well as erasing the erasure flag for the corrected demodulated data. Therefore, more errors can be erasure-corrected in data where burst errors are likely to occur.
The erasure correction method according to the present invention comprises a step of performing the erasure correction by the correcting codes at least once before performing the erasure correction using the erasure flag, a after performing the erasure correction, or before and after the erasure correction. Therefore, the erasure correction having a further higher correction capability is realized.
An erasure correction circuit according to the present invention for erasure-correcting an error by plural error correcting codes comprises: a demodulator for demodulating modulated data into demodulated data having the plural error correcting codes added thereto, as well as detecting a demodulation error and setting an erasure flag; a demodulated data memory for retaining the demodulated data; an erasure flag memory for retaining the erasure flag; an error corrector for erasure-correcting errors in demodulated data which is read from the demodulated data memory, including the demodulation error indicated by the erasure flag, as well as outputting error position information of corrected demodulated data; and an erasure flag eraser for receiving the error position information, and instructing the erasure flag memory to erase the erasure flag for the corrected demodulated data. Therefore, the erasure correction having a correction capability higher than that of the prior art which uses the demodulation error as an erasure flag only for the erasure correction of an inner code is realized.
In the erasure correction circuit of the present invention, the error corrector reads the demodulated data for each of the error correcting codes to perform the correction; the erasure flag eraser instructs the erasure of the erasure flag for each of the correcting codes; and the error corrector uses an erasure flag which is not erased at the correction processing by a precedent correcting code, thereby erasure-correcting an error at a correction processing by a subsequent correcting code. Therefore, the erasure flags are not incorrectly set to correct demodulated data and the erasure correction having a higher correction capability is realized.
In the erasure correction circuit of the present invention, the error corrector initially reads the demodulated data for each codeword of the outer code, thereby performing the erasure correction. Therefore, more errors can be erasure-corrected in data where burst errors are likely to occur.
In the erasure correction circuit of the present invention, the error corrector reads the demodulated data for each codeword of the inner code after the initial erasure correction by the outer code, and erasure-corrects an error using an erasure flag which is not erased at the erasure correction by the outer code. Therefore, the erasure correction having a further higher correction capability is realized.
In the erasure correction circuit of the present invention, the error corrector initially reads the demodulated data for each codeword of the inner code to perform erasure correction, thereafter reads the demodulated data for each codeword of the outer code to erasure-correct an error using an erasure flag which is not erased at the erasure correction by the inner code, and reads again the demodulated data for each codeword of the inner code to erasure-correct an error using an erasure flag which is not erased at the erasure correction by the outer code. Therefore, more errors can be erasure-corrected in data where burst errors are likely to occur.
In the erasure correction circuit of the present invention, the error corrector performs the erasure correction by the correcting codes, at least once before performing the erasure correction using the erasure flag, after performing the erasure correction, or before and after the erasure correction. Therefore, the erasure correction having a further higher correction capability is realized.